In the build-up of layers of a semiconductor device, features are lithographically defined by placing photoresist onto an underlying layer and selectively exposing the resist to a pre-selected wavelength of light. The exposure causes a photo-sensitive chemical reaction to occur in the photoresist, which creates patterns that determine features in underlying layers. Thereafter, the photoresist is developed, which removes unwanted areas and creates a desired feature pattern for the underlying layer. The patterned photoresist is then used as an etch mask to transfer the pattern into the underlying layer; or onto a hardmask atop the underlying layer that performs the pattern transfer.
The photoresist must be free of defects before etching commences. One mechanism that can degrade the integrity of a photoresist film is a chemical reaction between the film and an amorphous carbon layer that is sometimes formed between the substrate to be etched and the photoresist. Typically, the carbon layer serves as an etch hardmask useful in the fabrication of numerous devices such as, for example a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) used in conventional CMOS (Complementary Metal Oxide Semiconductor) integrated circuits, or stacked-gate structures used in non-volatile memory devices for storing electrical charges. In one application the amorphous carbon hardmask material is formed over a gate electrode film. Photoresist film is deposited atop the hardmask layer; and a pattern is formed within the resist. The resist is developed to expose the hardmask material to the pattern. The hardmask is then etched, and the remaining photoresist is removed, leaving the hardmask material to serve as the mask to transfer the desired pattern to the gate electrode film by etch.
Amorphous carbon is an advantageous choice for hardmask material because of its etch resistant (low etch rate) properties when compared to the typical materials used for underlying gate stacks such as polysilicon. Other hardmask materials including silicon nitride film, oxide film, or a silicon oxynitride film may also be advantageous. The amorphous carbon typically is deposited using a PECVD process. If placed into direct contact with the photoresist film, amorphous carbon can poison the photoresist by allowing nitrogen species from the carbon layer to diffuse into the film and neutralize photogenerated acid species. The neutralization results in a failure to remove the resist in the desired region during the develop step which uses mild basic chemistry, thereby leading to the formation of a region of undesired resist—also known as an “extra pattern” of resist. Extra resist patterns are defects since the pattern on the photolithographic mask is not transferred to the wafer with perfect fidelity. The extra resist patterns can distort the shape of printed features, which can affect conductivity and adversely impact the feature's influence on underlying layers, as by affecting channel length, for example. If the extra patterns are sufficiently large—in the vicinity of 300 nm in diameter when the space between adjacent lines is only 200 nm, shorting can occur with resultant yield losses.
One way to avoid the defects of photoresist poisoning is to separate the resist and amorphous carbon layers with an intermediary or “capping” layer. These are typically formed by applying a layer of SiON between the resist film and the amorphous carbon layer. The SiON layer is about 200–400 Angstroms in thickness, and the amorphous carbon layer is >100 Angstroms in thickness, preferably in a range of 300–700 Angstroms. Capping layers formed only of SiON in the PECVD plasma environment, however, have a tendency to develop pinholes on the order of 10–20 nm in major (lateral) dimension. One explanation as to causation is poor step coverage or insufficient nucleation over the underlying film. The pinholes allow species such as nitrogen to migrate through and interact with photoresist, thereby causing extra pattern defects as described above.
A possible solution is an alternative intermediary material to the current SiON, which has less or preferably no inclination to form pinholes. Another possible solution is to create a “capping stack” consisting of multiple layers of different materials including SiON, to thwart pinhole formation.
Realizing a successful alternative capping layer or capping stack requires more than simply producing a non-porous barrier between the amorphous carbon and the resist layer. Meeting all of the following requirements is essential for an effective capping stack. The capping stack must be an effective etch masking layer for the amorphous carbon serving as a hardmask. Further, the amorphous carbon must retain its hardmask properties for the substrate layer beneath it, which can be polysilicon, a polymer, an oxide, or many other different materials such as SiCOH used in the back end of line/interconnect levels, bare silicon, or a nitride placed on bare silicon, or a metallic gate electrode such as TiN.
Moreover, material chosen for each of the layers in the capping stack must be formable with fairly precise optical properties including the real and imaginary components of refractive index, in order to assure that anti-reflection and CD swing minimization objectives are achieved. CD swing may be defined as the variation in printed dimension in the photoresist arising from differences in photoresist thickness caused by underlying topography. Interference effects due to back reflection from the underlying substrate can modulate the retained dose in the photoresist, thereby changing the printed dimension. A typical target is <0.5% reflectivity into the resist at the photolithography wavelength of choice which by current industry standards are 248 nm, or 193 nm; and (in the future) 157 nm. Finally, the capping stack layers should be producible in the existing PECVD process without having to materially alter the deposition chamber or remove the wafers from the chamber.
Complicating the containment of photoresist defects is the fact that the size of the extra patterns will impact different device technologies differently, depending on the physical layout and pitch. For example, an extra pattern 400 nm in width is unlikely to cause significant yield loss when the spacing between lines is, say, 500 nm. However, as device dimensions continue to shrink, the same defect can have a catastrophic yield impact when spacings are reduced to 300 nm. Also, in a given technology, features on circuits may have locations consisting of patterns with increased/decreased pattern density which may be affected differently due to similar reasons as above. Further, photoresist patterns used for contact and interconnect “via” definition—usually known as “dark field” masks owing to the reduced overall open area—may possibly be affected to a lesser extent than, say, a gate layer mask “bright field” for the same extent of defects likely to cause unintended patterns.